B. Sc Degree Examination, November 2018
Part III - Allied
Physics II - COMPUTER AND ORGANIZATION ARCHITECTURE
Time: 3 Hrs
Max Mark: 75M
Part A
1. What do you mean by 'BUS'.
2. Define CPU and ALU.
3. Name the methods of performance parameters
4. What is DRAM and SRAM.
5. What is Data.
6. What are the drawbacks of Programmed I/O and Interrupt driven I/O.
7. Mention the important categories of data types .
8. What is fetch cycle?
9. What are the features provided from I/O subsystems to processors?
10. Differentiate 'thread' and 'process'.
Part B
11. (a) Explain the main structural components of a computer. (or)
(b) Explain the main structural components of a processor.
12. (a) How does disk cache improve the performance of the processor? (or)
(b) Discuss the properties shared by semiconductor main memory.
13. (a) Distinguish memory mapped I/O and isolated I/O. (or)
Part III - Allied
Physics II - COMPUTER AND ORGANIZATION ARCHITECTURE
Time: 3 Hrs
Max Mark: 75M
Part A
1. What do you mean by 'BUS'.
2. Define CPU and ALU.
3. Name the methods of performance parameters
4. What is DRAM and SRAM.
5. What is Data.
6. What are the drawbacks of Programmed I/O and Interrupt driven I/O.
7. Mention the important categories of data types .
8. What is fetch cycle?
9. What are the features provided from I/O subsystems to processors?
10. Differentiate 'thread' and 'process'.
Part B
11. (a) Explain the main structural components of a computer. (or)
(b) Explain the main structural components of a processor.
12. (a) How does disk cache improve the performance of the processor? (or)
(b) Discuss the properties shared by semiconductor main memory.
13. (a) Distinguish memory mapped I/O and isolated I/O. (or)
(b) Discuss the characteristics of I/O
channels.
14. (a) Explain logical
data in types of operand. (or)
(b) Outline the requirements of processor
organization.
15. (a) List the
characteristics of symmetric multiprocessors. (or)
(b) Discuss the terms involved in Non Uniform
Memory Access (NUMA).
PART C – (3 × 10 =30)
Answer any THREE questions.
16. Explain
bus structure.
17. Discuss
Cache memory principles.
18. Explain
the DMA function with its block diagram.
19. Explain
in detail, the register organization.
20. Discuss
the approaches to explicit multi threading.
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